1. Field of the Invention
The field of the invention relates to data storage and in particular, to the storage and access of data in semiconductor memories.
2. Description of the Prior Art
As semiconductor memory devices become ever smaller, operational problems associated with their small scale geometries become more significant. A particular problem is data reliability, wherein due to the small scale of the semiconductor memory device a data value written to the memory device may not be stable and can later be read as a different value. For example a data value may be written as “1”, but may be later read as “0”, due to a problem in the storage of that value.
The reliability of such semiconductor memory devices is further challenged by the drive to operate such devices at ever lower voltages. As a consequence, these semiconductor devices operate in a regime where two dimensional electric field effects and other effects relating to the physics of the operation of small scale circuit elements (such as gate tunnelling and band-to-band tunnelling) play an ever greater role in disturbing the desired operation of these devices.
Error correction schemes to counteract such error phenomena are known, however these techniques may be of limited applicability, since only a limited number of errors can be corrected. For example, error correction schemes in memory devices typically have a limit of one bit error per word, the occurrence of more than one bit error in a word leading to the inability of the error correction scheme to identify where the error to be corrected is located.
One approach to this problem is to use multiple memory instances which duplicate one another. However, this approach can have the drawback of a significant increase in power consumption, which is an undesirable attribute for contemporary semiconductor devices.
Another approach, in the context of SRAM-based FPGAs is discussed in “On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs”, Kastensmidt et al., DATE conference 2005, pp. 1290-1295. Here a triple redundancy scheme is used wherein an error in one memory cell can be identified with reference to the other two instances of this memory cell. However, the quantity of extra logic circuitry required to enable the voting mechanism which decides on the correct value is an undesirable feature.
Another approach to this problem in the context in SRAMs is discussed in “SRAM Word-oriented Redundancy Methodology using Built In Self-Repair”, J. H. Lee et al., in IEEE International ASIC Conference 2004, pages 219-222. In this paper a word oriented redundancy is used which can be used by a Built In Self-Repair technique to correct errors. However, this technique also requires an undesirable quantity of additional logic to be provided in order to implement the BISR technique.
A further problem that is known to be encountered by such small scale semiconductor memory devices is that of read-disturb. This phenomenon can occur when the voltage at which the semiconductor device is operating is so low that the process of reading the values stored in a memory cell can cause the value itself to be changed. One known approach to this problem is disclosed in “An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage”, H. Pilo et al, JSSC, April 2007. Here the implemented scheme writes back to the read cell, so that it can correct any read-disturb that has been caused.
Commonly assigned patent application publication US2008/0165609 discloses a memory array which is responsive to a repair signal to operate either in a normal mode or a repair mode.
“Quality of a Bit (QoB): A New Concept in Dependable SRAM”, Fujiwara et al., 9th International Symposium on Quality Electronic Design, 2008, pp. 98-102, describes a technique for protecting a data value stored in a memory cell, but requires a dedicated storage cell to be provided to implement this technique.
It will be recognised that providing mechanisms to increase the reliability of such semiconductor memory devices will necessarily come at the expense of some area on the silicon device, yet it would be desirable to provide a technique to increase the reliability of a semiconductor memory device, in a flexible and efficient manner, without the need for significant additional circuitry taking up valuable space in the semiconductor device.